The present invention relates generally to bistable, reflective Cholesteric displays. More specifically, the present invention relates to a graphic controller for active matrix addressed bistable, reflective Cholesteric displays. Advantageously, a corresponding system and method of operation for driving the bistable, reflective Cholesteric displays are also disclosed.
Liquid crystal displays (LCD""s) have been widely adapted for use in a number of products such as digital watches and clocks, laptop computers, and information and advertising display signs. LCD""s are generally classified according to their drive scheme, e.g., passive matrix LCD""s and active matrix LCD""s.
With respect to passive matrix LCD""s, the display includes a thin layer of liquid crystal material sandwiched between two transparent panels. An electrode array comprising a first set or plurality of parallel oriented electrode segments (row electrode segments) disposed on an inwardly facing side of one panel and a second set or plurality of parallel oriented electrode segments (column electrode segments) which are perpendicular to the row electrode segments disposed on an inwardly facing side of the other panel is provided. The row and column electrode segments are spaced apart by spacer material and the liquid crystal material is filled in the spaced apart region between the panels.
Display picture elements or pixels are defined by regions of liquid crystal material adjacent the intersections of aligned electrodes of the horizontal and vertical electrode segments of the electrode array. Upon application of a suitable electric field, a pixel in a reflective display will assume either a reflective or a non-reflective state. A pixel, pi,j, formed at the overlapping or intersection of the ith row electrode and the jth column electrode is subject to an electric field resulting from the potential difference between a voltage applied to the ith row electrode segment and a voltage applied to the jth column electrode segment.
Recent advances in liquid crystal material research have resulted in the discovery of bistable chiral nematic (also called cholesteric) liquid crystal materials. Cholesteric liquid crystal materials are able to maintain a given state (reflective or non-reflective) without the need for the constant application of an electric field. When data or an image displayed on a display is to be changed, the display driver ciruitry will update the display corresponding to the changes.
If the panel furthest from the viewer is painted with a black substrate, a pixel with a low reflectance will appear as a black area to the viewer. If the liquid crystal material has a light color appearance (such as yellow) in its highly reflective state, a pixel in a high reflectance state will appear to the viewer as an iridescent colored area on a black background.
Bistable Cholesteric liquid crystal displays (hereinafter Ch-LCD) have received considerable attention of display designers and manufacturers in recent years for portable applications because of their advantageous optical properties and low power consumption. It will be appreciated that this interest has resulted in the introduction of a significant number of products employed in a wide variety of applications. Moreover, this interest has produced various improvements in bistable, reflective Cholesteric displays in terms of optical properties such as brightness, contrast, and full color.
The most prevalent technique for driving the Ch-LCD is by passive matrix addressing. In that case, display driver circuitry is coupled to the vertical and horizontal electrodes of the electrode array. Operating under the control of a logic and control unit, the display driver circuitry energizes the row and column electrodes with appropriate voltage waveforms such that an appropriate voltage across each pixel is generated. The voltage across a pixel will either cause it to remain in its present state of reflectance or change its state of reflectance. The image generated by the display pixels may be modified by changing the state of selected pixels. In this way, text or image data can be presented for viewing.
In the invention disclosed in U.S. Pat. No. 5,748,277 (the ""277 patent), which is entitled xe2x80x9cDynamic Drive Method and Apparatus for a Bistable Liquid Crystal Display,xe2x80x9d a method and display driver circuitry for speeding the rate of updating a 1,000 row cholesteric liquid crystal display was disclosed. The ""277 patent is incorporated herein in its entirety by reference. An updating time of approximately one-second for a 1000 row display was achieved. By simultaneously addressing multiple rows of the display with a pipelining scheme, the overall updating time for the display was kept at one second.
With suitable thresholds, zero voltage bistability enables low cost passive matrix addressing for Ch-LCD. However, the slow material response time and the unique switching scheme required by the bistable display makes it difficult for a Ch-LCD to achieve video rate updates on a large format display. While a significant amount of effort has also been devoted to improving the update speed (in milliseconds (ms)) of the bistable, reflective Cholesteric displays, results to date have been less than optimal, as discussed in greater detail immediately below.
The dynamic and electro-optical responses of a typical, bistable reflective Ch-LCD are illustrated in FIGS. 1A and 1B. As shown in FIG. 1a, an AC voltage in the form of pulses varying from 0V to 50V is applied to the display and the reflectance is plotted; in FIG. 1b, reflectance is plotted as a function of time.
Referring to FIG. 1a, the reflectance is initially high, i.e., before any voltage is applied. Upon the application of the voltage pulse, the display is switched into the Homeotropic State and the reflectance becomes very low. Once the voltage pulse is switched off, the reflectance gradually increases to the maximum. The rise time of the display is about 250 ms, as illustrated in FIG. 1b. It will be appreciated that in video applications, this long rise time will cause unpleasant image ghosting.
It will be noted that the final display reflectance versus the voltage amplitude is shown in FIG. 1a. More specifically, there are two initial (stable) states: the planar (higher reflectance) state and the focal conic (lower reflectance) state. It will also be noted that there are several threshold voltages. When the applied voltage is below V1, the display will stay in either of its initial states after the pulse. When the voltage increases from V1 to V2, the reflectance of the initially ON display will decrease to a minimal value. The reflectance of the initially OFF display begins to increase when the voltage is above V3xe2x80x2 and the reflectance reaches the maximum when the voltage is above V4. The reflectance of the initially ON display begins to increase its reflectance when the voltage is above V3 and the reflectance reaches the maximum when the voltage is above V4xe2x80x2. Therefore, for voltage between V2 and V3, the display is switched to the low Reflectance State regardless of its initial state; for voltage above V4, the display is switched to the high reflective state regardless of its initial state. Note that there are regions in the voltage response diagram, such as between V1 and V2, where there exists stable partially reflecting states providing the opportunity for gray scale addressing.
Basic concepts and schemes for passive matrix addressing of a bistable reflective cholesteric display are disclosed in U.S. Pat. Nos. 5,251,048 and 5,644,330, which patents are incorporated herein by reference. A basic requirement for passive matrix addressing is that:
[(V4xe2x88x92V3)/2] greater than V1.
This requirement can be met by adjusting the display process and associated material parameters. However, this requirement also limits the adaptation of certain display configurations, which configurations may have other benefits.
Several drive methods have been developed in an effort to improve the speed at which the cells of a bistable, reflective Cholesteric display can be changed between the ON and OFF states. For example, specialized drive schemes and erase sequences can be employed to improve the speed of a conventional drive system to approximately 3 ms/row, as described in U.S. Pat. No. 5,644,330. In contrast, dynamic driving of the bistable, reflective Cholesteric display makes use of the fast homeotropic-transient planar transition, which results in a drive speed of approximately 0.5 ms/row. The dynamic driving technique is described in greater detail U.S. Pat. No. 5,748,277 and in the paper by X. Y. Huang et al. in the SID greater than 95 Technical Digest, p. 347 (1995).
It should be noted that, due to the use of a passive matrix addressing scheme, the user always sees a black scan line sweeping across the entire screen. The development of a cumulative drive scheme removes the black scan line; however, it is limited by how many rows that can be addressed in one frame period. Additional details regarding the cumulative drive are disclosed in U.S. Pat. No. 6,133,895, which patent is incorporated herein be reference in its entirety for all purposes. All of these limitations are inherent in the passive matrix addressing methods used in addressing and driving bistable, reflective Cholesteric displays.
An active matrix addressing method for bistable, reflective Cholesteric displays has been proposed which makes use of the planar and the homeotropic states. Further details regarding this proposed method are available in the article by J. Y. Nahm et al. presented in the proceedings of at Asia Display ""98 (18th International Display Research Conference, Seoul, Korea), p. 979 (1998), and by Y. Kawata et. al. in Proceedings Of The International Research Conference 97 (Toronto, Canada), p. 246 (1997). However, in that addressing scheme, the bistability of the Cholesteric display was sacrificed, which, in turn, resulted in an increase in the power required to drive the active matrix Cholesteric displays. Furthermore, it will be noted that it is not possible to provide a gray scale using the previously proposed active matrix addressing method.
Before discussing the present invention in greater detail, it should be mentioned that all of the patents and articles cited within the instant specification are incorporated herein by reference.
What is needed is a drive method and corresponding circuitry for an active matrix addressed bistable, reflective Cholesteric display which avoids the relatively low update speed limitation associated with such displays. Moreover, what is needed is a drive method and corresponding circuitry for an active matrix addressed bistable, reflective Cholesteric display which maintains the low power benefit of Cholesteric display technology. What is also needed is a combination including an active matrix addressed bistable, reflective Cholesteric display and associated drive circuitry. It would be beneficial if the combination could be included into a plurality of different products.
Based on the above and foregoing, it can be appreciated that there presently exists a need in the art for a graphic controller for an active matrix addressed bistable, reflective Cholesteric display which overcomes the above-described deficiencies. The present invention was motivated by a desire to overcome the drawbacks and shortcomings of the presently available technology, and thereby fulfill this need in the art.
According to one aspect of the present invention, an active matrix addressed Cholesteric display is achieved by careful design of the drive scheme, implemented via the driver and controller, to thereby allow the Cholesteric display to maintain its superior optical performance, e.g., high brightness, high contrast, flicker-free viewing, and the low power bistability, i.e., only the pixels that need to be changed are updated. The improved active matrix addressed bistable, reflective Cholesteric display according to the present invention advantageously provides a video rate compatible, scan-line free update capability.
According to one aspect, the present invention provides graphics controller for a color display system having a bistable liquid crystal display (LCD) for displaying a plurality of pixels arranged in a matrix, the graphics controller including a memory device for storing color data and status bits corresponding to each of the pixels, and a generating device for generating voltage data corresponding to the pixels based on the color data and the status bits for each of the pixels. In an exemplary case, the bistable LCD is a Cholesteric LCD. Preferably, the generating device has a first mode of operation in which the data corresponding to the pixels is generated for each corresponding pixel and a second mode of operation in which no data is generated; the generating device switches from the first operating mode to the second operating mode when all of the status bits for all of the pixels are zeros.
According to another aspect, the present invention provides a graphics controller for a low power color display having a bistable liquid crystal display (LCD) including a plurality of cells arranged in a matrix, each cell corresponding to a pixel, including a memory which stores color data and status bits corresponding to all of the pixels, and circuitry which generates voltage data corresponding to the pixels based on the color data and the status bits for each of the pixels. Preferably, the circuitry generates the voltage data for a corresponding pixel when the status bits correspond to a non-zero binary number. Most preferably, the circuitry has a first mode of operation in which the voltage data corresponding to the pixels is generated for each corresponding pixel and a second mode of operation in which no voltage data is generated, the circuitry switching from the first operating mode to the second operating mode when all of the status bits for all of the pixels are zeros. Advantageously, the circuitry generates the data for a corresponding pixel N times to thereby permit application of the generated pixel data to the LCD N time, where N is an integer established by the status bits.
According to yet another aspect, the present invention provides a graphics controller for a low power color display including a bistable liquid crystal display (LCD) having multiple cells arranged in a matrix, each cell corresponding to a pixel. Preferably, the graphics controller includes a memory which stores color data and status bits corresponding to a plurality of pixels, status logic which generates the status bits responsive to receipt of color data for a respective one of the pixels, a data generator which generates voltage data corresponding to the pixels based on the color data and the status bits for each of the pixels, and driver circuitry which generates voltage signals responsive to receipt of the voltage data for each of the pixels, wherein the LCD is responsive to the voltage signals produced by the driver circuitry. In an exemplary case, the bistable LCD comprises a Cholesteric LCD. Advantageously, the graphics controller includes a power supply which provides power to the driver circuitry, and a power manager which turns the power supply ON when the data generator is in a first operating mode and which turns the power supply OFF when the data generator is in a second operating mode. In an exemplary embodiment, the data generator cycles between the first and second operating modes based on the integer value of the status bits. In another exemplary embodiment, the graphics controller includes status logic which decrements the status bits of a corresponding one of the pixels each time the voltage data for that corresponding pixel is generated by the data generator, and replaces the status bits with decremented status bits after the voltage data is output by the data generator, permitting the data generator to generate the voltage data for a corresponding pixel N times and thereby permit application of the voltage signal corresponding to the pixel data to the LCD N time, where N is an integer established by the status bits.